1. Field of the Invention
The present invention relates to digital electronics, and more specifically, to a background calibrating pipelined analog-to-digital converter.
2. Description of the Prior Art
Pipelined analog-to-digital converters (ADCs) are widely used in applications such as video imaging systems, digital subscriber loops, Gigabit Ethernet transceivers, and wireless communications. Pipelined analog-to-digital (A/D) conversion offers a good trade-off among power, speed, and integrated circuit die area, and is suitable for implementing high-resolution ADCs operating at sampling frequencies in the order of megahertz.
FIG. 1 illustrates a state-of-the-art pipelined ADC 10. The ADC 10 includes a series of multiplying digital-to-analog converter (MDAC) stages 12, 14, 16, which may or may not be identical, and an encoder 18. The first MDAC stage 12 receives an analog signal V1 and outputs a digital code D1 representative of the analog signal V1 according to a predefined precision. Successive stages 14, 16 output digital codes D2, D3 according to successive amplified residual signals V2, V3 of the first and second stages 12, 14 respectively. Each successive stage digitizes the residue of the previous stage, so accordingly, the digital output D1 of the first stage 12 contains the most significant bits (MSBs) while the output Dp of the last stage 16 contains the least significant bits (LSBs). The encoder 18 arranges the outputs D1, D2, D3 of the stages 12, 14, 16 to produce a consistent digital representation D0 of the input analog signal V1.
FIG. 2 illustrates a typical MDAC 20 used for the MDAC stages 12, 14, 16 of the ADC 10 of FIG. 1. The MDAC 20 includes an internal ADC 22, a digital-to-analog converter (DAC) 24, an adder 26, and an amplifier 28. In operation, an analog input Vj received from a previous stage (or as an input signal itself) is quantized by the ADC 22 producing a digital code Dj that is an estimation of Vj. The DAC 24 generates a corresponding analog signal Vjda(Dj) that is then subtracted from the input signal Vj by the adder 26. The residue outputted by the adder 26 is amplified by the amplifier 28 according to a gain factor Gj. The output Vj+1 of the MDAC 20 can be described as follows:
VjH=Gjxc3x97[Vjxe2x88x92Vda(Dj)]xe2x80x83xe2x80x83(1) 
Accordingly, the input of the pipelined ADC 10 can then be expressed as:                               V          1                =                              V            1            do                    +                                    V              2              do                                      G              1                                +                                    V              3              do                                                      G                1                            ⁢                              G                2                                              +          ⋯          +                                    V              p              do                                                      G                1                            ⁢                              G                2                            ⁢                              xe2x80x83                            ⁢              ⋯              ⁢                              xe2x80x83                            ⁢                              G                                  p                  -                  1                                                              +          Q                                    (        2        )            
where Q=VP+1/(G1G2 . . . GP) is the quantizing error of the entire A/D conversion. The encoder 18 of FIG. 1 calculates the digital output D0 by subtracting Q from V1. The signals Vjda and gains Gj are design parameters. In addition, it is well known that the conversion characteristics of the internal ADC 22 in the pipeline stages 20 have no effect on the digital output D0.
In CMOS applications, most A/D pipeline stages are realized with switched-capacitor (SC) MDACs, which include comparators, operational amplifiers (opamps), switches, and capacitors as described above. FIG. 3 shows a prior art radix-2 1.5 bit SC MDAC 30 having a conversion characteristic as illustrated in FIG. 4. The MDAC 30 includes comparators 32, 34, an encoder 36, switches 38, first and second capacitors 40, 42 having respective capacitances C and C, and an operational amplifier 44. During a sample phase, when a first clock is high, the switches 38 marked 1 are exclusively closed, and the signal Vj is sampled on the first and second capacitors 40, 42. Accordingly, the digital code output is determined as xe2x88x921, 0, or +1 according to the comparators 32, 34 comparing the signal Vj with +0.25V and xe2x88x920.25Vr references respectively. Conversely, during a hold phase, when a second clock is high, the switches 38 marked 2 are exclusively closed. During the hold phase, the output Vj+1 can be expressed as:                               V                      j            +            1                          =                              (                          1              +                                                C                  s                                                  C                  f                                                      )                    xc3x97                      [                                          V                j                            -                                                                    C                    s                                                                              C                      s                                        +                                          C                      f                                                                      ⁢                                                      V                    p                                    ·                                      D                    j                                                                        ]                                              (        3        )            
assuming linear behavior of the capacitors 40, 42, and an ideal operational amplifier 44 with infinite DC gain and zero input offset voltage. In practical application, the capacitances Cf and Cs of the capacitors 40, 42 are desired to be the same. However, due to capacitance mismatches (C fnot equal to C) and input offset voltage of the operational amplifier 44 in implementation, the pipelined ADC 10 must be calibrated for accurate results. Regarding calibration, there is a fundamental trade-off between ADC operation speed and accuracy, which depends on the matching properties of devices such as MOSFETs and capacitors. The accuracy of an MDAC is dictated by the input offset voltages of the comparators and the operational amplifier, and the exact values of the capacitor ratios. To overcome this speed-accuracy trade-off, several self-calibration techniques have been developed. Although the calibration can be performed in the analog domain, entirely digital approaches are preferred in deep sub-micron technologies, due to reduced cost of added digital circuitry. In addition, in digital self-calibration schemes the necessary modification to the MDACs is noncritical, and thus, the analog signal paths suffer little performance degradation.
Conventional self-calibration schemes require reconfiguration of MDACs, which cannot be performed without interrupting normal A/D operation. Thus, in applications that can afford little idle time, ADCs are calibrated only during an initial power-on state. Any power-on calibration may later become invalid because of variations in supply voltage and temperature. To address this problem, several background calibration schemes have been developed that enable an ADC to continuously calibrate internal MDACs to track environmental changes while simultaneously performing normal conversion without resolution degradation.
There are several well-known approaches to background calibration. The xe2x80x9cskip-and-fillxe2x80x9d algorithm randomly skips A/D cycles to calibrate the MDACs and fill in the missing outputs by nonlinear interpolation, as described in U.K. Moon and B.S. Song, xe2x80x9cBackground digital calibration techniques for pipelined ADCsxe2x80x9d, IEEE Trans. Circuits Syst. II, vol. 44, pp. 102-109, February 1997 and S. U. Kwak, B. S. Song, and K. Bacrania, xe2x80x9cA 15-b, 5-Msample/s lowspurious CMOS ADCxe2x80x9d, IEEE J. Solid-State Circuits, vol. 32, pp. 1866-1875, December 1997, which are incorporated herein by reference. However, the bandwidth of the input signal needs to be limited for the interpolator to achieve good results. Moreover, if a multi-bit MDAC is used in a pipeline stage, it is possible to estimate the MDACs conversion errors in normal A/D operation using information on the MDACs mismatch pattern. But, without the MDACs gain error information, this approach is only suitable for high gain pipeline stages.
Background calibration can also be achieved by using an extra MDAC to replace the one under calibration, as described in J. M. Ingino and B. A. Wooley, xe2x80x9cA continuously calibrated 12-b, 10-MS/s, 3.3V A/D converterxe2x80x9d, IEFE J. Solid-State Circuits, vol. 33, pp. 1920-1931, December 1998, which is incorporated herein by reference. However, the complexity of the required analog switching scheme can degrade speed performance of the analog signal path.
Another scheme proposed in J. Ming and S. H. Lewis, xe2x80x9cAn 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration,xe2x80x9d IEEE J. Solid-State Circuits, vol. 36, pp. 1489-1497, October 2001, which is incorporated herein by reference, is only capable of correcting gain error while adding significant analog and digital hardware.
Finally, an example of a self-calibrating reversible pipeline ADC/DAC is disclosed in U.S. Pat. No. 5,929,796, which is incorporated herein by reference.
The conventional background calibration schemes are in need of improvement with respect to nonlinear effects due to MDAC gain error, input offset voltage, and output errors in the digital-to-analog conversion.
It is therefore a primary objective of the claimed invention to provide an MDAC stage, a background-calibrating pipelined ADC, and a related method to overcome the above-described shortcomings of the prior art.
Briefly summarized, an MDAC stage according to the claimed invention includes a sub-analog-to-digital converter for converting an analog signal received at an input node to a digital code, an amplifier, and a first capacitance selectively connected between the input node and the amplifier input and between the amplifier input and the amplifier output. The claimed MDAC further includes a plurality of second capacitances connected in parallel selectively between the input node and the amplifier input and between a corresponding plurality of digital reference signals and the amplifier input. The plurality of digital reference signals comprises digital signals corresponding to the digital code and a first calibration signal. During a sample phase the first capacitance is connected between the input node and the amplifier input and the plurality of second capacitances are connected in parallel between the input node and the amplifier input. During a hold phase the first capacitance is connected between the amplifier input and the amplifier output and the plurality of second capacitances are connected in parallel between the plurality of digital reference signals and the amplifier input.
According to the claimed invention, a pipelined ADC incorporating a series of claimed MDAC stages includes a multiplier connected to the output of the last MDAC stage of the series. The multiplier is capable of determining a product of the last MDAC stage output and a second calibration signal corresponding to the first calibration signal. Further provided are a low-pass filter connected to the multiplier for filtering output of the multiplier and outputting a DC component, and an encoder for receiving output of the MDAC stages and generating a digital output signal, and for compensating the digital output signal with the DC component.
According to the claimed invention, a method includes steps of sampling an input analog signal on a first capacitance and a plurality of second capacitances of an MDAC stage during a sample phase, applying a first calibration signal to a second capacitance of the MDAC stage during a hold phase, and finally, filtering the first calibration signal from the digital output of the pipelined analog-to-digital converter.
It is an advantage of the claimed invention that the plurality of second capacitances and the first calibration signal allow for calibration without interruption of normal A/D conversion.
It is a further advantage of the claimed invention that the plurality of second capacitors results in no significant extra capacitive loads so that operating speed is not degraded.
It is a further advantage of the claimed invention that nonlinear effects due to gain error, input offset voltage, and output errors in the digital-to-analog conversion are reduced.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.